1. Field of the Invention
The present invention relates to solid-state image sensors, specifically to charge detection elements of image sensors detecting any kind of radiation such as but not limited to visible light.
2. Discussion of the Related Art
A typical image sensor senses radiation by converting impinging radiation into charges that are integrated (collected) in sensor pixels. During or after completion of an integration cycle, the charge is converted into a voltage that is supplied to the output terminals of the sensor.
Typical basic pixel architectures are built around 3 or 4 transistors, the so called 3T and 4T architectures which are shown in FIGS. 1 and 2 labelled 100 and 200 respectively. With reference to FIGS. 1 and 2, in these architectures a photodiode PD 101 converts received radiation into a charge, and a first transistor M1, labelled 102, is dedicated to resetting the sensing node, while two further transistors, M2 and M3, labelled 104, 106, are dedicated to the selective readout of a signal voltage generated inside the pixel. A fourth transistor M4, labelled 108 and shown in the 4T configuration of FIG. 2, is provided to transfer signal charges from the radiation sensing element to a separate charge storage node.
Commonly, an integration capacitor Cint of the sensor, which stores a charge related to the impinging radiation, is provided by the parasitic capacitances of the source of transistor 102 and the gate of transistor 104 and the wiring between these components, all of which are usually tried to be kept small, so as to increase the sensitivity of the image sensor. This capacitance is represented by capacitor 110 in FIGS. 1 and 2.
Both architectures may be limited in their dynamic range by the charge handling capacity, also called pixel Full Well (FW), which is defined as the amount of charge that can be stored by the integration capacitor Cint 110 without exceeding the voltage range that can be handled by the reset transistor M1 102, the transfer transistor M4 108 in the case of architecture 200 of FIG. 2, the readout transistors M2 104 and M3 106, and the subsequent stages of signal processing. Since a larger dynamic range allows for better image quality, one of the targets of image sensor design is to increase the charge handling capacity of the pixel.
One approach for increasing the charge handling capacity is to increase the capacitance of the integration capacitor, Cint 110, through the addition of an extra capacitor in parallel. An example of this solution, called 4TC, is described by H. Rhodes in “CMOS imager technology shrinks and image performance”, published on pages 7-18 in “2004 IEEE Workshop on Microelectronics and Electron Devices”.
While in this solution this extra capacitive charge handling capability is permanently effective, an alternative approach is described in the “2003 Workshop on CCDs and Advanced Image Sensors” in a paper titled “Programmable sensitivity image sensor with multi-capacitance CMOS pixels” from Ryutaro Oi of University of Tokyo, and such an image sensor 300 is shown in FIG. 3. Here, the additional capacitor C2, labelled 302, is connected to a radiation sensing node VPix through a select transistor M5 304 controlled by a select signal SelC. Node VPix is a node at which the charge generated by photodiode 101 is stored. Principally the pixel can be operated in two modes: one high full well mode with transistor M5 304 turned ON and thus capacitor C2 added in parallel to capacitor Cint to give a larger full well; the other with transistor M5 304 turned OFF to give a higher sensitivity while compromising the capacity of the full well. But, according to the authors, this pixel also allows operation with high full well and high sensitivity in one and the same integration frame, by turning ON and OFF the select transistor M5 304 during integration. However, during readout, the charge stored by the capacitor Cint must be read out first, then transistor M5 304 is turned ON again to allow the charges stored by capacitor C2 to be read out.
It can be a further requirement in various applications to provide a global shutter to reduce motion distortion, especially where the time to read the sensor plane is long compared to typical motion distortion times, such as in the case of multi-megapixel sensors. A solution that has been proposed is depicted in FIG. 4, which shows an image sensor 400 similar to the circuit of FIG. 2, except that reset transistor M1 102 is connected directly to photodiode 101 in image sensor 400 and the integration capacitor CInt 110 of FIG. 2 has been replaced by a charge handling capacitor CFD 402. An example of such a circuit is, for example, disclosed in paper titled “A high speed camera system based on an image sensor in standard CMOS technology”, Hillebrand, M et al. As shown in FIG. 4, the transfer gate transistor M4 304 is used here to separate the charge storage capacitor CFD from the radiation-sensing diode at the end of the integration period. While the signal stored by capacitor CFD can be held until the pixel is read out, the next integration period can be launched by applying a reset pulse to the gate of M1 thus resetting the radiation-sensing diode voltage to the reset voltage ready to be discharged by the subsequent integration phase.
Thus this solution allows the operation of a global shutter mode, but does not allow operation with variable sensitivity, as provided by the solution in FIG. 3. On the other hand, the selectable sensitivity solution in FIG. 3 does not allow the operation of a global shutter mode. In certain demanding applications both modes are required together in one device.